About

I am currently an Assistant Professor at the University of Rennes.
I am located at Lannion at the ENSSAT engineering school.

  • Teaching: ENSSAT
  • Group: D4 - Architecture
  • mail: bertrand.le-gal(at)irisa.fr
  • Research: IRISA / INRIA
  • Team: TARAN
  • Phone: +33 (0)2 96 46 90 00

A few information about my background:

  • 2005: PhD in Computer Sciences (University of Bretagne)
  • 2005 ATER at ENSSAT (University of Rennes)
  • 2006 Assistant Professor at Bordeaux-INP / IMS lab.
  • 2006 Accreditation to supervise doctoral research (HDR) (UB)
  • 2023 Assistant Professor at ENSSAT (University of Rennes)

Resume

Bertrand LE GAL received MS (2001) and MS Ph (2002) degrees in Computer Sciences from the University of South Britany (UBS), France. After this training, he obtained a PhD degree (2002-2005) in Computer and Information Sciences from the University of South Britany (UBS), France. His PhD, focusing on high-level synthesis methodologies (HLS tools such as GAUT), was carried out under the supervision of Professors Eric MARTIN and Emmanuel CASSEAU. In 2005-2006, he worked as an ATER at the University of Rennes in the IRISA/INRIA laboratory, as part of the R2D2 team at Lannion (ENSSAT), working on similar research topics.

After 4 years of in Computer-Aided Design, High Level Synthesis, digital circuits and telecommunication systems, in 2006, he joined the IMS laboratory and the Bordeaux-INP engineering school (ENSEIRB-MATMECA). He was then an Associate Professor with the IMS Laboratory, in the CSN research team. During this period, his research interests include digital design using high-level synthesis tools and efficient software implementation on High-Performance Computing devices (CPU, SIMD, GPU, FPGA) of Error Correction Code decoding algorithms such as LDPC, turbo-codes or polar codes. Since 2019, he extended its research activities to RISC-V processor design and more precisely on security and efficiency aspects according to application domains. He is the author or co-author of 32 peer-reviewed publications in selective international journals and more than one hundred peer-reviewed articles in international conferences these topics and holds 1 patent in hardware design domain and developed 2 licensed softwares (high-throughput and low-latency 5G LDPC decoders on x86 devices). He received in February 2023 the accreditation to supervise doctoral research from University of Bordeaux, France.

In September 2023, he moved to Lannion (ENSSAT) and he is currently an Associate Professor with the IRISA/INRA Laboratory (Universitée de Rennes). He is a member of the “D3 - Architecture” group and is more precisely attached to the TARAN team.

Some numerical facts

Some numerical data related to my research work since the beginning of my PhD. It includes my research work at LabSTICC in Lorient (10/2002-09/2006), at IMS in Bordeaux (10/2006-09/2023) and since September 2023 at IRISA/INRIA in Lannion.

PhD students

Past PhD students

Journal articles

Conference articles

Master students

Patents and licensed softwares

ANR projects

Industrials projects

Research Skills

Below is a list of the skills I've developed through the various research activities I've carried out since my recruitment to Bordeaux in 2006. It should be noted that the list is not exhaustive and that I have tried to quantify as best I can my level of competence in each field...

Hardware design (RTL and VHDL)100%
High-Level Synthesis (HLS)100%
Processor (RISC-V) design80%
Co-design on AMD Zynq90%
Error Correction Codes90%
Design methodology90%
SIMD optimization100%
GPU optimization80%

Teaching Skills

Since 2006, I've had the chance to teach in various fields. However, my expertise lies in the following areas:.

C/C++ languages100%
VHDL language and FPGA technology100%
microcontroller75%
High-Level Synthesis (Vitis HLS) 100%
Parallel programming (SIMD, OpenMP, CUDA & GPUs) 90%
Design test and verification (VHDL/C)80%

Teaching activities

ENSSAT - Teaching activities (2023-...)

[1A - S1] digital basics

  • to do...

[2A - S4] VHDL and FPGA design

  • to do...

[2A - S4] Low-power design

  • to do...

[2A - S4] Low-power design

  • to do...

[3A - S5] Software compilation

  • to do...

ENSEIRB-MATMECA - Teaching activities (2006-2023)

[EN325] Conception Numérique Avancée

[SE301] Calcul Haute Performance pour les Systèmes Embarqués (HPEC)

[EN201] Synthèse VHDL

[EN201/202] VHDL de Synthèse et FPGA (NEXYS-4)

[PG208] Conception Objets et UML

Publication list

Journal papers

C. Moniere and B. Le Gal and E. Boutillon. Real-time energy-efficient software and hardware implementations of a QCSP communication system. Journal of System Architecture (JSA), ELSEVIER, 141:102933, August 2023 ( , ).

B. Le Gal, V. Pignoly, and C. Jégo. High‐performance hard‐input LDPC decoding on multicore devices for optical communication links. Journal of System Architecture (JSA), ELSEVIER, 137:102832, April 2023 ( , ).

Y. Delomier, B. Le Gal, J. Crenne, and C. Jego. Model‐based design of hardware SC polar decoders for FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 13(2):27, June 2020 ( , ).

Y. Delomier, B. Le Gal, J. Crenne, and C. Jego. Model‐based design of flexible and efficient LDPC decoders on FPGA devices. Journal of Signal Processing Systems (JSPS), Springer, 92:727–745, February 2020 ( , ).

A. Cassagne, O. Hartmann, M. Léonardon, C. Leroux, R. Tajan, O. Aumage, D. Barthou, T. Tonnellier, V. Pignoly, B. Le Gal, and C. Jégo. AFF3CT: A fast forward error correction toolbox!. SoftwareX, Elsevier, November 11 2019 ( , ).

B. Le Gal and C.Jego. Low‐latency and high‐throughput software turbo‐decoders on multi‐core architectures. Annals of Telecommunications, Springer, 75:27–42, August 2019 ( , ).

B. Le Gal and C. Jego. High‐throughput FFT‐SPA decoder implementation for non‐binary LDPC codes on mulitcore target. Journal of Signal Processing Systems, Springer, 92:37–53, March 2019 ( , ).

B. Le Gal, C. Leroux, and C. Jego. High‐performance software implementation of SCAN decoders for polar codes. Annals of Telecommunications, Springer, 73(5):401–412, April 2018 ( , ).

I. Debbabi, B. Le Gal, N. Khouja, F. Tlili, and C. Jego. Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding. Journal of Signal Processing Systems, Springer, X(X), pages 1-17, September 2017 ( , ).

I. Debbabi, B. Le Gal, N. Khouja, F. Tlili, and C. Jego. Real time LP decoding of LDPC codes for applications requiring high correction performances. IEEE Wireless Communications Letters, X(X):Y–Z, October 2016. ( , ).

B. Le Gal, L. Reveillere, Y-D. Bromberg and J. Solanki. A flexible SoC and its methodology for parser-based applications. ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10 (1), September 2016 ( , ).

T. Tonnellier, C. Leroux, B. Le Gal, C. Jego, B. Gadat and N. Van Wambeke. Lowering the Error Floor of Turbo Codes With CRC Verification. IEEE Wireless Communications Letters, vol. 5 (4), pages 404–407, August 2016 ( , ).

B. Le Gal and C. Jégo. High-throughput multi-core LDPC decoders based on x86 processor. IEEE Transactions on Parallel and Distributed Systems, vol. 27 (5), pages 1373–1386, May 2016 ( , ).

I. Debbabi, B. Le Gal, N. Khouja, F. Tlili and C. Jego. Fast Converging ADMM Penalized Algorithm for LDPC Decoding. IEEE Communications Letters, vol. 20 (4), pages 648–651, April 2016 ( , ).

B. Le Gal and C. Jégo. High-throughput LDPC decoder on low-power embedded processors. IEEE Communications Letters, vol. 19(11), pages 1861–1864, September 2015 ( , ).

B. Le Gal, C. Leroux and C. Jego. Multi-Gb/s software decoding of Polar Codes. IEEE Transactions on Signal Processing (TSP), pages 349 – 359, January 2015 ( , ).

B. Le Gal and C. Jégo. >GPU-like on-chip system for decoding LDPC codes. ACM Transactions on Embedded Computing Systems (TECS), vol. 13(4), pages 1-19, November 2014 ( , ).

B. Le Gal, C. Jégo and J. Crenne. A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices. IEEE Embedded System Letters, vol. 6(2), pages 29 – 32, June 2014 ( , ).

B. Le Gal, C. Jego and C. Leroux. A Flexible NISC-Based LDPC Decoder. IEEE Transactions on Signal Processing (TSP), vol. 62(10), pages 2469–2479, May 2014 ( , ).

F. Duhem, F. Muller, W. Aubry, B. Le Gal, D. Negru, and P. Lorenzini. Design space exploration for partially reconfigurable architectures in real-time systems. Journal of Systems Architecture (JSA), Elsevier, vol. 59(8), pages 571–581, September 2013 ( , ).

M. Kthiri, B. Le Gal, P. Kadionik, and A. Ben Atitallah. A very-high throughput deblocking filter for h264/AVC standard. Journal of Signal Processing Systems, Springer, vol. 73(2), pages 189–199, November 2013 ( , ).

B. Le Gal and C. Jego. Softcore processor optimization according to real-application requirements. IEEE Embedded Systems Letters, vol. 5(1), pages 4–7, March 2013 ( , ).

B. Belean, M. Borda, B. Le Gal, and R. Terebes. FPGA based system for automatic cDNA microarray image processing. Computerized Medical Imaging and Graphics journal, Elsevier, vol. 36(5), pp. 419–429, July 2012 ( , ).

E. Casseau and B. Le Gal. Design of multi-mode application-specific cores based on high-level synthesis. Integration, the VLSI Journal, Elsevier, vol. 45(1), pp. 9–21, January 2012 ( , ).

N. Delaunay, M. Abid, B. Le Gal, D. Dallet, C. Rebai, N. Deltimple, E. Kerherve, and D. Belot. Mixed cartesian feedback for zero-IF WCDMA transmitter. Analog Integrated Circuits and Signal Processing Journal, Springer, vol. 73(3), pp. 909–917, December 2012 ( , ).

J. Mercadal, L. Reveillere, Y-D. Bromberg, B. Le Gal, T. F. Bissyande, and J. Solanki. Zebra : Building efficient network message parsers for embedded systems. IEEE Embedded Systems Letters, vol. 4(3), pp. 69–72, September 2012 ( , ).

K. Grati, N. Khouja, B. Le Gal, and A. Ghazel. Power consumption models for decimation FIR filters in multistandard receivers. VLSI Design, Hindawi, 2012 (Article ID 870546), 15 pages, March 2012 ( , ).

B. Le Gal and L. Bossuet. Automatic low-cost IP watermarking technique based on I/O mark insertions. Design Automation for Embedded Systems, Springer, vol. 2012(16), pp. 71–92, May 2012 ( , ).

K. Grati, N. Khouja, B. Le Gal, and A. Ghazel. High-level design flow targeting real multistandard circuit designer requirements. Journal of Communication and Computer, David Publishing, vol. 8, pp. 335–346, May 2011 ( , ).

B. Le Gal and E. Casseau. Word-length aware DSP hardware design flow based on high-level synthesis. Journal of Signal Processing Systems, Springer, vol. 62(1), pp. 341–357, March 2011 ( , ).

B. Le Gal and E. Casseau. Latency-sensitive high-level synthesis for multiple word-length DSP design. Journal on Advances in Signal Processing (JSPS), Eurasip, vol. 2011 (Article ID 927670), 11 pages, January 2011 ( , ).

B. Le Gal, E. Casseau, and S. Huet. Dynamic memory access management for high-performance DSP applications using High-Level Synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16(11), pp. 1454–1464, November 2008 ( , ).


Book chapter(s)

To do... ( , ).


Conference article(s)

To do... ( , ).


Workshop presentation(s)

To do... ( , ).

Current PhD students

Magnam dolores commodi suscipit. Necessitatibus eius consequatur ex aliquid fuga eum quidem. Sit sint consectetur velit. Quisquam quos quisquam cupiditate. Et nemo qui impedit suscipit alias ea. Quia fugiat sit in iste officiis commodi quidem hic quas.

Antoine SIEBERT (2021-2024)

"Contribution à l’implémentation d’algorithmes d’IA pour application de radiocommunications dans un contexte embarqué durci"

funding IMS and THALES SIX [CIFRE], co-directed G. Ferré.

Oussama AIT SIDI ALI (2022-2025)

"Virtualisation d’un récepteur de télémesure multi-missions"

funding funding IMS and SAFRAN [CIFRE], co-directed with R. Tajan.

Léo PAJOT (2023-2026)

"Implémentation d’un processeur soft-core à exécution dynamique de binaires exploitant un fort parallélisme au niveau instruction"

funding IMS and KEYSOM [CIFRE], co-directed with S. Rokicki.

Léa VOLPIN (2023-2026)

"Développement et optimisation d'un système radar automobile"

funding IMS and NXP [CIFRE], co-directed with G. Ferré.

Victor LEVALLOIS (09/2023-..)

"Développement et optimisation d'un système radar automobile"

funding INRIA (défis), co-directed with P. Peterlongo and Y. Dufresne.

Abdallah Abdallah (12/2023-...)

"Simplified non-binary decoders"

funding MNRT and , co-directed with E. Boutillon.

Robinson CARRERE (01/2024-...)

"Conception d’un récepteur de communications numériques pour l’internet des objets par satellites en orbite basse"

funding Région Aquitaine, co-directed with G. Ferré.

Next PhD students

Magnam dolores commodi suscipit. Necessitatibus eius consequatur ex aliquid fuga eum quidem. Sit sint consectetur velit. Quisquam quos quisquam cupiditate. Et nemo qui impedit suscipit alias ea. Quia fugiat sit in iste officiis commodi quidem hic quas.

Matthieu MAGNANT (04/2024-...)

"Développement de systèmes embarqués pour les réseaux IoT par satellites en orbite basse"

funding IMS and EutelSat [CIFRE], co-directed with G. Ferré.

PhD students writing their thesis

Magnam dolores commodi suscipit. Necessitatibus eius consequatur ex aliquid fuga eum quidem. Sit sint consectetur velit. Quisquam quos quisquam cupiditate. Et nemo qui impedit suscipit alias ea. Quia fugiat sit in iste officiis commodi quidem hic quas.

Mael TOURRES (2019-2023)

"Conception automatisée de circuits numériques pour la couche physique de la 5ème génération"

funding Bordeaux-INP and LabSTICC, co-directed with C. Chavet and P. Coussy.

Hugues ALMORIN (2020-2023)

Software/hardware system modeling and design framework for systems-on-a-chip

funding IMS and ARELIS [CIFRE], co-directed with C. Jégo.

Clémence GILLET (2020-2023)

"Optimisation de l’implémentation sur FPGA de réseaux de neurones événementiels pour le traitement de signaux biologiques"

funding IMS [MNRT], co-directed with A. Vincent and S. Saighi.

Denis SHEMONAEV (2020-2023)

"Intégration de fonctions d'apprentissage pour le traitement vidéo avec la plateforme matérielle NATvision

funding MS and EMG2 [CIFRE], co-directed co-directed with C. Jégo.

Unfinished PhD thesis

Magnam dolores commodi suscipit. Necessitatibus eius consequatur ex aliquid fuga eum quidem. Sit sint consectetur velit. Quisquam quos quisquam cupiditate. Et nemo qui impedit suscipit alias ea. Quia fugiat sit in iste officiis commodi quidem hic quas.

Thomas NIEDDU (09/2022-08/2023)

"Sécurisation d’architecture par la gestion dynamique de microdécodage d’instructions"

funding MS and EMG2 [CIFRE], co-directed with S. Pillement.

Past PhD students

Camille MONIERE (2020-2023)

"Conception matérielle d’un démodulateur CCSK couplé à des décodeurs canal non-binaires"

funding IMS and LabSTICC [ANR QCSP], co-directed with E. Boutillon.

abc

Vincent PIGNOLY (2017-2021)

"Implémentation de nouveaux schémas de codage efficaces pour les communications optiques satellitaires"

funding IMS and Airbus D&S, co-directed with C. Jego.

abc

Yann DELOMIER (2016-2020)

"Conception à base de modèles de décodeurs ECC pour des applications 5G 3GPP à l'aide de la HLS"

funding IMS [MNRT], co-directed with C. Jego.

abc

Hayfa THAMEUR (2014-2019)

"ADMM-LP decoding of LDPC convolutional codes : from algorithm to implementation"

funding IMS and Tunisia, co-directed with N. Khouja et F. Tlili.

abc

Guillaume DELBERGUE (2015-2017)

"Modeling complex TLM based communications for SoCs in SystemC language"

funding IMS and GreenSoC [CIFRE], co-directed with C. Jego.

abc

Thibaud TONNELLIER (2013-2017)

"Evaluation and hardware implementations of novel approaches for turbo-coding"

funding IMS and Thales Aliena Space, co-directed with C. Jego and C. Leroux.

abc

Imen DEBBABI (2013-2017)

"LP decoding of LDPC codes: from algorithm to implementation"

funding IMS and Tunisia, co-directed with N. Khouja et F. Tlili.

abc

Jigar SOLANKI (2010-2014)

"Approche générative conjointe logicielle-matérielle au développement du support protocolaire}{d’applications réseaux"

funding IMS and LaBri [CNRS], co-directed with L. Reveillere et D. Bromberg.

abc

Aurélien RIBON (2009-2012)

"Improving the design verification methodologies in EDA tools for silicon debug"

funding IMS [MNRT], co-directed with D. DALLET.

abc

Willy AUBRY (2008-2012)

"Real time high-definition video stream adaptation on FPGA"

funding IMS and LaBri [ANR ArdMahn], co-directed with D. NEGRU, F. KRIEF et D. DALLET.

abc

Moez KTHIRI (2009-2012)

"Evaluation and implementation of optimized hardware accelerators for H.264/AVC standard"

funding IMS and LaBri [CNRS], co-directed with P. KADIONIK and H. LEVY.

abc

Nadia KHOUJA (2007-2011)

"Power optimization methodology for digital multi-standard communication circuits"

funding IMS and Tunisia, co-directed with K. GRATI and A. GHAZEL.

abc

Past Master of Science (MSc) students

Matthieu MAGNANT (2023)

"Implantation temps réel d'un système de détection de trames Lora sur cible Zynq UltraScale+

Thomas NIEDDU (2022)

"Intégration de mécanismes de sécurité CISC dans un processeur RISC-V

Léa VOLPIN (2022)

"Conception et évaluation de systèmes d'émission Lora et QCSP pour l'IoT

Oussama AIT SIDI ALI (2021)

"Développement d'une plateforme SDR à base d'USRP pour la modulation CCSK

Salma IZOUGGARHAN (2021)

"Implantation d'algorithmes de decodage LDPC sur le multi-coeurs Kalray's MPPA

Florian LOUPIAS (2020)

"Développement d'une plateforme SDR temps réel pour le reception ADSB"

Clémence GILLET (2020)

"Implantation de réseaux de neurones événementiels sur circuit FPGA"

Mael TOURRES (2019)

"Hardware implementation of a dynamically reconfigurable RISC-V core on FPGA"

Rémi FUMERON (2019)

"Application of HLS-based methodology to runtime power-amplifier correction"

Safouane NOUBIR (2018)

"Evaluation of HLS tool performances for the generation of biomedical real-time systems"

Vincent PIGNOLY (2017)

"Evaluation of HLS-based methodology for the design of NB-LDPC decoders"

Chaima BOUZOUITA (2016)

"Hardware implementation of LDPC-CC decoders for ASIC/FPGA targets"

Imen NAJEH (2015)

"Breaking LDPC error floors using re-decoding techniques"

Rima TABESSI (2014)

"Evaluation and implementation of digital processing algorithm on FPGA targets for biomedical applications"

Guillaume DELBERGUE (2012)

"Modeling and simulation in SystemC of complex computation systems"

Alexis AULERY (2012)

"Design and implementation of the digital system to control PA in a W-CDMA context"

Walid SANAA (2011)

"ASIC implementation of a digital system for power amplifier mismatch compensation in W-CDMA context"

Mohammed ABID (2010)

"Design and implementation of a digital Cartesian feedback for power amplifier mismatch correction"

Jérémie VIGUIER (2010)

"Watermarking of digital hardwares generated using HLS tools"

Julien BEZINE (2010)

"Automated methodology for hardware generation of message parser automation"

Zied BERRIRI (2009)

"Design and implementation of a digital processing algorithm for correct TIADC mismatches"

Maha JEBALIA (2008)

"Design and implementation of a digital decimation filters for Sigma-Delta modulators"

Haïfa FARES (2006)

"Design and implementation of a digital decimation filters for multi-standard communication systems"

ANR research projects

ANR ARDMAHN (2009-2012)

"Architecture Reconfigurable Dynamiquement et Méthodologie pour l'Autoadaptation en Home Networking"

ANR NAND (2016-2019)

"Noise Against Noise Decoder"

ANR QCSP (2019-2023)

"Quasi Cyclic Small Packet"

ANR SEC-V (2022-2025)

"Secure RISC-V cores"

GitHub repositories

High-Throughput LDPC decoders on x86 device (2012)

"Conception matérielle d’un démodulateur CCSK couplé à des décodeurs canal non-binaires"

funding IMS and LabSTICC [ANR QCSP], co-directed with E. Boutillon.

High-Throughput LDPC decoders on GPU device (2014)

"Conception matérielle d’un démodulateur CCSK couplé à des décodeurs canal non-binaires"

funding IMS and LabSTICC [ANR QCSP], co-directed with E. Boutillon.

High-Throughput LDPC decoders on ARM device (2013)

"Conception matérielle d’un démodulateur CCSK couplé à des décodeurs canal non-binaires"

funding IMS and LabSTICC [ANR QCSP], co-directed with E. Boutillon.

adsb-receiver (2013)

"Conception matérielle d’un démodulateur CCSK couplé à des décodeurs canal non-binaires"

funding IMS and LabSTICC [ANR QCSP], co-directed with E. Boutillon.

adsb-observer (2013)

"Conception matérielle d’un démodulateur CCSK couplé à des décodeurs canal non-binaires"

funding IMS and LabSTICC [ANR QCSP], co-directed with E. Boutillon.

Mandelbrot-SIMD-and-GPU (2013)

"Conception matérielle d’un démodulateur CCSK couplé à des décodeurs canal non-binaires"

funding IMS and LabSTICC [ANR QCSP], co-directed with E. Boutillon.

AVX2_shift_and_rotate_si256 HLS-Sorter-on-FPGA HLS-Sorter-on-FPGA-int32_t SIMD_bitset_rotation AVX2_float_functions SFML-simple-maze french_word_sudent

Contact

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Location:

6 rue de Kerampont, 22305 Lannion, FRANCE

Call:

+33 (0)2 96 46 90 00

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